A. gate signal is always present
B. gate signal must be removed
C. gate signal should present but can be removed
D. none of the above.
A. < latching current but greater than holding current and gate signal is 0.
B. less than holding current.
C. < latching current but greater than holding current and gate signal is present.
D. both (A) and (B).
A. 600 V/µs
B. 800 V/µs
C. 1200 V/µs
D. 1000 V/µs
A. High power phase control
B. High power current control
C. Low power current control
D. Low power phase control
A. Vc1 > Vc2 > Vc3 when Ig1 > Ig2 > Ig3.
B. Vc1 > Vc2 > Vc3 when Ig1 < Ig2 < Ig3.
C. Vc1 = Vc2 = Vc3 any value of Ig.
D. Vc1 > Vc2 > Vc3 when Ig1 ≥ Ig2 &Atil
A. SIT
B. SITH
C. GTO
D. SCR
A. Forward voltage triggering
B. Gate triggering
C. dV / dt triggering
D. Thermal triggering
A. forward blocking mode
B. reverse blocking mode
C. both forward and reverse blocking mode
D. forward conduction mode
A. Recovery is only 5 µs
B. Recovery is only 50 µs
C. Dog is carried out
D. None of these
A. CB
B. Snubber circuit
C. Voltage clamg device
D. Fast acting current limiting device (FACL fuse)