A. NOT gate
B. OR gate
C. AND gate
D.None of the above
A. NOT gate
B. OR gate
C. AND gate
D.None of the above
A. 19
B. 12
C. 27
D.21
A. 2TTL
B. 5TTL
C. 8TTL
D. 10TTL
A. 10 CPS
B. 120 CPS
C. 12CPS
D. None of the above
III. 1010 + 1101 = 11111
A. I and II
B. II and III
C. III only
D. II and III
A. Weighted code
B. Cyclic redundancy code
C. Self-complementing code
D. Algebraic code
A. 1 at any input causes the output to be at logic 1
B. 1 at any input causes the output to be at logic 0
C. 0 any input causes the output to be at logic 0
D. 0 at any input causes the output to be at logic 1
A. an astable MV
B. a bistable MV
C. a latch
D. a monostable MV
A. all the inputs to the gates are “1”
B. all the inputs are ‘0’
C. either of the inputs is “1”
D. all the inputs and outputs are complemented
A. have lower fabrication area
B. can be used to make any gate
C. consume least electronic power
D. provide maximum density in a chip